For Students
Atomic Layer Etching Breakthrough: APS Technology Targets 14 Ångstrom Semiconductor Nodes Without EUV
The semiconductor industry, driven by the demand for smaller, more efficient chips, has relied on extreme ultraviolet (EUV) lithography to scale down to 2-nanometer processes. However, the high cost and complexity of EUV equipment, costing hundreds of millions, have limited its profitability for
5 min read
Socionext Releases White Paper on High-Bandwidth Switch Fabric SoC Design Methodology
Socionext has announced the release of a white paper titled "Optimizing High-Bandwidth Switch Fabric SoC Design: Minimizing Implementation Risks, Ensuring First-Pass Success, and Accelerating Time-to-Market." The document addresses the increasing complexity of switch fabric System-on-Chip (SoC) d
2 min read
RISC-V Multi-Core and Many-Core Architectures-part2
RISC-V Multi-Core and Many-Core Architectures -Continued Many-Core RISC-V ArchitecturesScaling to Many-Core Systems
47 min read
RISC-V Multi-Core and Many-Core Architectures
The open-source RISC-V instruction-set architecture has moved from academic curiosity to mainstream technology in barely a decade, shipping more than 10 billion cores by 2022 and expanding at a pace that outstrips earlier ISAs such as x86 and ARM. Market analysts forecast an add
65 min read
IEEE BHTC 2026 to Explore AI for Sustainability in Bangalore
The 6th IEEE Bangalore Humanitarian Technology Conference (BHTC) is scheduled to take place from March 27 to 29, 2026, at The Chancery Pavilion, Residency Road, Bangalore, India. Organized by the IEEE Bangalore Section in collaboration with the Bengaluru Science and Technology Cluster (BeST), the
2 min read
AI-Powered Questa One at Siemens U2U EDA Verification Forum Focuses on Making DV Engineer Smarter
At the Siemens EDA Users2Users Verification Forum 2025 held in Bangalore on 3rd July 2025, Siemens EDA showcased its AI based advancements in VLSI design and verification, with a spotlight on its AI-powered Questa One platform. The event, attended by industry leaders and verification engineers, h
4 min read
Ruchir Dixit’s Cricket Analogy Inspires Teamwork in VLSI Chip Verification at Siemens EDA Forum
At the Siemens EDA Users2Users Verification Forum 2025 in Bangalore, Ruchir Dixit, Vice President and Country Manager of Siemens EDA, opened with a compelling cricket trophy winning analogy, drawing parallels between Royal Challengers Bengaluru’s (RCB) 2025 IPL victory and the teamwork esse
5 min read
VLSI Design: LVS (Layout Versus Schematic) in OpenROAD Environment -p3
Continued from VLSI Design: LVS (Layout Versus Schematic) in OpenROAD Environment -p2 LVS Script Development Basic LVS Script Structure
30 min read
Understanding RISC-V architecture: A detailed guide to the open-source ISA revolution- P3
Continued from Understanding RISC-V architecture: A detailed guide to the open-source ISA revolution- P2 Design
19 min read
Understanding RISC-V architecture: A detailed guide to the open-source ISA revolution- P2
Continued from
61 min read
Understanding RISC-V architecture: A detailed guide to the open-source ISA revolution
For decades, the landscape of general-purpose and embedded computing has been dominated by two proprietary instruction set architectures: Intel’s x86 and Arm’s RISC-based architecture. Th
65 min read
VLSI Design: LVS (Layout Versus Schematic) in OpenROAD Environment -p2
Continued from VLSI Design: LVS (Layout Versus Schematic) in OpenROAD Environment OpenROAD Architecture <
63 min read
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