Analog computing array for edge AI
In the rapidly evolving landscape of artificial intelligence (AI) and machine learning (ML), the demand for efficient and scalable computing solutions has never been higher.
Traditional digital computing architectures, while powerful, often struggle with energy efficiency and computational density. Addressing these challenges, researchers at the Indian Institute of Science (IISc) in collaboration with Washington University in St. Louis have developed ARYABHAT, a groundbreaking field-programmable analog computing array designed specifically for edge AI applications.
ARYABHAT-1 is a next-generation analog computing chipset designed to target AI and ML applications at the edge. Presently, such computations are achieved by application-specific digital accelerators, which utilize spatial arrays of parallel processing elements to significantly improve performance and energy efficiency compared to general-purpose platforms. This work focuses on building the first-of-its-kind technology scalable reconfigurable analog processor that can be fully scaled down to sub-nanometer process nodes.
Most electronic devices, particularly those that involve computing, use digital chips because the design process is simple and scalable. “But the advantage of analog is huge. You will get orders of magnitude improvement in power and size,” explains Chetan Singh Thakur, Assistant Professor at the Department of Electronic Systems
Engineering (DESE), IISc, whose lab is leading the efforts to develop the analog chipset. In applications that don’t require precise calculations, analog computing has the potential to outperform digital computing as the former is more energy efficient.
Key Contributions of this work include:
MAC based near-memory crossbar computational tile: Design of near-memory crossbar computational tile for analog multiply and accumulate (MAC) operation, enabling scalable computations in analog under diverse operational conditions.
Digital-like Analog Synthesis Flow: Proposition of a standard cell-based digital-like analog synthesis flow to rapidly design analog machine learning systems.
Re-configurable Interconnect Matrix: Design implementation of a digitally programmable current-mode analog interconnect fabric to enable reconfigurability and pro-grammability across multiple tiles.
ARYAFlow Mapper: Developing ARYAFlow, a mapper designed for mapping and optimizing machine learning algorithms for use on accelerator chipsets, generating bit streams for the chip’s programmability.
ARYATest Framework: Developing ARYATest, an open source test framework built with the PyVISA package,facilitating automated functional verification of machine learning algorithms on the accelerator chipset.
Algorithms Implementation: Demonstrating the implementation of a standard 4-layer neural network, a variant of SVM classifier, and a parallel FIR filter bank using the
accelerator chipset.
ARYABHATTA-1 stands for “Analog Reconfigurable Technology and Bias-scalable Hardware for AI Tasks”.
Such chipsets can be beneficial for applications based on AI such as object or speech recognising apps including Alexa. It can also be beneficial for applications requiring very efficient parallel computations.
Digital chips are used in many electronic devices, especially those that require computers because the design process is scalable and straightforward.
Chip Micrograph. Credits: NeuRonICS Lab, DESE, IISc
The current research has barely scratched the surface of high-performance analog accelerator designs. To date, the power density and performance benefits of analog designs remain unmatched to their digital counterparts. Such analog accelerators can not only achieve similar performance for the much lesser area but are also orders of magnitude energy-efficient. However, designing and scaling such analog compute
systems is often very challenging due to nonlinear artifacts including bias dependency,
mismatch and process technology dependency of design. With the aim of overcoming these analog shortcomings, the objective of this work was to create a truly scalable analog computing framework starting from algorithm to system prototype and demonstrate its feasibility on Machine Learning and Deep Neural Nets.
This work was started in late 2019 where we started with the development of a novel analog computing framework called Shape-based Analog Computing. This novel framework allowed us to design analog circuits based on approximate shape rather than precise computation. Utilizing this Shape-based Analog Computing, we created robust analog standard cells for widely used computational functions used in standard ML tasks We then utilized these analog standard cells to create high performance analog computing cores.
Demonstration of real time chip testing
According to researchers, ARYABHAT is capable of being configured with several machine learning architectures. For instance, with the digital CPUs. It has the potential to function reliably on different temperature ranges.
The ARYABHAT chip is a standard CMOS 180nm process technology. It may be noted that multiple copies of the computational tile were fabricated for test purposes.
The functionality of the circuit modules has been verified using the test measurement setup. The test chip was mounted on a custom IC test board, and the test vectors were generated using a PYNQ-Z2 FPGA board which used a Python-based interface to control the digital inputs and outputs. High-precision analog test equipment was directly
interfaced with the test chip using the ARYATest framework, also controlled by the PYNQ-Z2 FPGA board. To accurately determine the region of operation, the transistors were first characterized for some fixed circuit parameters (such as the aspect ratio of the transistor, spline count S, etc.). This section shows the results of the SAC computational core and the interconnect fabric at different operating conditions.
"With ARYABHAT, IISc researchers are not just pushing the boundaries of analog computing; they are redefining the future of edge AI with innovation and efficency."
ARYABHAT represents a significant leap forward in the field of analog computing for AI and ML applications. Its innovative design, combined with the flexibility of field-programmable architectures, positions it as a powerful tool for edge computing.
As AI continues to evolve, solutions like ARYABHAT will play a crucial role in meeting the growing demands for efficient and scalable computing resources.
A reconfigurable multi-tile analog chipset called ARYABHAT for use in ML and edge computing applications. We demonstrated the chipset’s performance under various power and performance specifications and simultaneously across different applications highlighting its scalability and reconfigurability. In addition, we provided a complete system stack, including an algorithm mapping tool (ARYAFlow) and an analog testing framework (ARYATest) to complete the computing ecosystem.The design flow and synthesis of analog machine-learning system similar to digital ASIC implementation. the operational performance parameters of the overall chip and report some of the widely used metrics for ML accelerators. It can also be noted that the current version of ARYABHAT has constraints in terms of memory availability and reconfigurability. This leads to a restricted range of CNNs and DNNs that can be implemented. Due to hese limitations, the FC neural network can implement up to 8 hidden layers, each having 156 hidden neurons. Finally, the output layer can have 256 neurons with all-to-all connectivity.
Additionally, when utilizing the architecture for CNN network, it is possible to employ a 2 × 2 kernel on a 3 × 3 matrix and other similar configurations which depend on how the
tiles are programmed, considering the restriction in kernel size. Nonetheless, if the chip possesses ample resources, its architecture is versatile enough to support a larger subset of ML and AI algorithms.
Future versions of ARYABHAT will expand resources, improve interconnect bandwidth,
upgrade the mapper to support more ML algorithms and implement a cluster configuration for improved scalability of DNNs.
This work was a collaborative effort by several researchers. The key contributors include Pratik Kumar, Ankita Nandi, Ayan Saha, Kurupati Sai Pruthvi Teja, Ratul Das, Shantanu Chakrabartty from the Department of Electrical and Systems Engineering, and Chetan Singh Thakur from the NeuRonICS Laboratory, Department of Electronic Systems Engineering at the Indian Institute of Science, Bengaluru. The team leveraged recent advances in margin-propagation-based approximate computing to design ARYABHAT, a field-programmable analog machine learning processor. This processor can be synthesized like digital field-programmable gate arrays (FPGAs) and features a fully reconfigurable tile-based modular analog architecture.
