Cadence and Intel Foundry have announced a multi-year expanded collaboration centered on Design Technology Co-Optimization (DTCO) for Intel's next-generation 14A process node one of the most advanced semiconductor manufacturing processes currently in development. The partnership combines Cadence's AI-driven EDA tools and design IP with Intel Foundry's process technology expertise, with the shared goal of helping chip designers achieve better performance, lower power consumption, and smaller die area on Intel 14A.
As semiconductor process nodes shrink below 2nm, the traditional approach of designing chips and then mapping them to a manufacturing process no longer works efficiently. At these dimensions, the design tools, the physical layout rules, the manufacturing process, and the circuit architecture are so tightly interdependent that they must be developed together iteratively and simultaneously. This is what DTCO means in practice.
When done well, DTCO produces process design kits (PDKs) and design flows that are genuinely optimized for each other resulting in chips that extract the maximum possible performance and efficiency from the underlying manufacturing process. When it is missing or shallow, customers end up leaving significant performance on the table even on an advanced node.
By formalizing this collaboration, Cadence and Intel are essentially working as a joint engineering team to ensure that Intel 14A's manufacturing capabilities and Cadence's design tools are fully aligned before customer tapeouts begin.
DTCO the core of the collaboration. Cadence and Intel will jointly optimize tools, design flows, and methodologies targeting Intel 14A, with the goal of delivering production-ready PDKs that enable chip designers to hit their performance, power, and area targets reliably and predictably.
IP Readiness Cadence will develop and validate its design IP standard cells, interface IP, memory compilers, and other reusable building blocks specifically for Intel 14A. Having pre-characterized, silicon-proven IP available at process launch dramatically reduces the time and risk for customers starting new designs on the node.
Design Enablement Cadence's agentic AI-driven EDA flows will be integrated into the Intel 14A design environment. Agentic AI in this context means AI systems that can autonomously execute multi-step design tasks running optimization loops, identifying layout issues, and making design decisions rather than simply assisting human engineers. This accelerates time-to-market and reduces the engineering effort required to bring a new chip to tapeout.
Intel Foundry is in the midst of an ambitious effort to re-establish itself as a leading-edge foundry competing with TSMC and Samsung. The credibility of that effort depends critically on having a mature, customer-ready design ecosystem not just a capable manufacturing process. A deep DTCO partnership with Cadence, the industry's leading EDA provider, directly strengthens that ecosystem story.
For Cadence, early and deep access to Intel 14A process data allows them to ensure their tools are fully validated and optimized for the node ahead of broad customer availability a competitive advantage in winning design starts on Intel Foundry.
For chip designers targeting HPC and mobile applications the two segments explicitly called out this collaboration means a more predictable path from design intent to silicon on one of the industry's most advanced process nodes.
