Imec has presented a 3D implementation of a charge-coupled device (CCD) memory with an IGZO channel, described as the first of its kind, at the 2026 IEEE International Memory Workshop (IMW). The device consists of vertical memory holes drilled through a stack of three word-lines that function as phase gates, with demonstrated transfer of charges across the gates at speeds exceeding 4 MHz.
The approach uses a 3D NAND-like architecture, which supports cost-effective fabrication and bit densities that exceed the DRAM limit. This positions the block-addressable 3D CCD as a candidate for CXL® type-3 buffer memory in AI applications, enabling the delivery of large data blocks to multiple processors through a high-bandwidth CXL® switch.
AI workloads have increased demand on DRAM-based memory systems, prompting exploration of alternative technologies to complement DRAM and high-bandwidth memory (HBM). CXL is one interface that provides access to larger memory pools shared across processors, differing from traditional DDR buses and creating opportunities for new memory types with distinct specifications.
In 2024, Imec introduced the conceptual 3D CCD with IGZO channel and demonstrated operation on a 2D proof-of-concept. The current 3D device integrates CCD registers into vertically aligned plugs formed by a punch-and-plug process through the three-word-line stack. Horizontal word-lines serve as gates, with bits represented by charges that are serially transferred and stored using a pulsed voltage scheme.
According to Maarten Rosmeulen, Program Director Storage Memory at Imec, reliable charge transfer occurs along the vertical IGZO channel at speeds over 4 MHz, with a few thousand charges transferred per cycle—sufficient for single-bit or multibit storage. The device operates at block-level access, unlike byte-addressable DRAM, aligning with AI workload requirements. It also features unlimited endurance, long data retention due to the IGZO material, and low-voltage operation based on charge storage.
The vertical IGZO channels achieve dimensions comparable to those in 3D NAND, with memory hole diameters of 80-120 nm. Ongoing work includes increasing the number of word-lines and optimizing the readout stage. Imec has stated readiness to advance the technology with industry partners for AI memory applications.
Figure: Schematic of the 3-word-line based 3D CCD structure: bottom gate (BG), center gate (CG), and top gate (TG), with source (S) at the bottom and drain (D) and image (b): cross-sectional TEM image showing 3 gate layers with a word-line pitch of 80 nm
