NEO Semiconductor Reports 3D X-DRAM Proof-of-Concept Results and Secures Strategic Investment

NEO Semiconductor announced successful proof-of-concept (POC) results for its 3D X-DRAM technology on April 23, 2026. The POC test chips validate manufacturability using mature 3D NAND-based processes and meet key DRAM performance benchmarks.

The company also announced a strategic investment led by Stan Shih, Founder and former Chairman and CEO of Acer and former Board Director of TSMC for over 20 years.

From left: Ray Tsay (Co-founder, NEO), Jack Sun (Dean, IAIS at NYCU), Stan Shih (Founder, Acer), Andy Hsu (Founder & CEO, NEO), Kun-Lin Lin (Deputy Director, TSRI), and Miki Huang (Co-founder, NEO)

The POC test chips demonstrate that 3D X-DRAM can be manufactured using existing 3D NAND infrastructure, including established equipment, materials, and cost-efficient processes. With 3D NAND already exceeding 300 layers in production, the results support development of high-density 3D DRAM.

3D X-DRAM proof-of-concept (POC) test chip demonstrating a scalable path toward next-generation, high-density AI memory

Key POC results include:  
- Read/write latency: <10 ns  
- Data retention: >1...