Siemens and NVIDIA announced that they have captured trillions of pre-silicon design cycles in days using Siemens’ Veloce proFPGA CS hardware-assisted verification and validation system combined with NVIDIA’s performance-optimized chip architecture. The companies reported capturing tens of trillions of cycles over a span of just a few days through their long-standing strategic partnership. The approach uses the scalable and performance-optimized hardware architecture of Veloce proFPGA CS together with NVIDIA’s chip architecture.
This capability supports verification and validation of highly complex AI/ML system-on-chip (SoC) designs. It allows designers and system architects to run and capture large numbers of verification cycles prior to first silicon availability, enabling them to process workloads that were previously considered difficult to achieve at this scale in short timeframes.
Jean-Marie Brunet, senior vice president and general manager of hardware assisted verification at Siemens Digital Industries Software, stated that the partnership is advancing hardware-assisted verification methodologies, including FPGA-based prototyping, to address demands from complex AI/ML SoCs. He noted that Veloce proFPGA CS combines a flexible and scalable hardware architecture with an advanced, easy-to-use implementation and debug software flow, providing solutions for single-FPGA IP validation as well as multi-billion gate chiplet designs.
Narendra Konda, vice president of hardware engineering at NVIDIA, said that as AI and computing architectures grow increasingly complex, semiconductor teams require high-performance verification solutions to validate massive workloads. The integration enables capture of trillions of cycles in days, offering the scale needed for reliability in next-generation AI.
FPGA-based prototype systems allow users to run pre-silicon verification workloads faster than simulation or emulation. However, current AI/ML designs require even greater capacity due to increasing chip and software complexity. Traditional verification tools such as simulation and emulation typically scale to millions or, at best, a few billion cycles in a practical timeframe. The ability to run trillions of design cycles in a short time has become critical to meet time-to-market and reliability requirements in the semiconductor industry.
Further details on Siemens’ Veloce proFPGA CS are available at: https://www.siemens.com/en-us/products/ic/hav/veloce-cs/profpga-cs/
The announcement is based on the official joint statement from Siemens and NVIDIA.
