Accellera Systems Initiative announced that its Board of Directors has approved the Standard for IP Abstraction for Clock and Reset Domain Crossing (CDC/RDC) Integration 1.0 for immediate release. The standard is now available for download from the Accellera website.
The standard addresses CDC/RDC verification needs in designs where signals cross asynchronous clock or reset boundaries, which can lead to metastability, glitches, and data reconvergence errors. Previously, analysis results and intent from different EDA tools could not be reused, requiring re-runs and manual translation during IP integration into SoCs.
This vendor-neutral standard defines a unified approach to capture CDC/RDC intent, allowing efficient signoff for IP providers and SoC integrators across multiple EDA vendors. It complements existing HDLs and IP-XACT methodologies by handling information beyond traditional HDL semantics, enabling portable interpretation across tools.
The development resolves a gap in IP-based SoC flows, where heterogeneous IP from various sources is verified with different tools and methodologies. By providing a common abstraction, the standard simplifies IP integration, reduces reliance on specific tools or expertise, and supports verification of complex designs.
Lu Dai, Chair of Accellera, stated that the standard provides interoperability for CDC and RDC verification and supports faster SoC signoff with greater confidence. He noted Accellera's role in collaborative standards and thanked volunteers from multiple companies and the working group leadership.
Lee Fueng Yap, Chair of Accellera's Clock Domain Crossing Working Group, explained that the standard offers a practical way to describe and share CDC/RDC intent independently of IP origin or tools used. This reduces reverification effort and improves confidence in scaling designs. He acknowledged co-founder Dammy Olopade and working group members.
Accellera will present the standard at DVCon U.S. 2026 in a tutorial titled “Breakthrough in CDC-RDC Verification Defining a Standard for Interoperable Abstract Model.” The session, scheduled for Thursday, March 5, 2026, from 9:00 a.m. to 12:30 p.m. at the Hyatt Regency Santa Clara in Ballroom D, will cover methodology, scope, and technical foundations, with registration available via the DVCon U.S. 2026 website.
The standard resulted from collaboration involving 157 members from 24 companies in the CDC Working Group.
Statements from participating companies include:
- Agnisys (Anupam Bakshi): The release advances standardization of CDC/RDC specifications for IP reuse, integration, and verification efficiency in heterogeneous SoCs.
- Blue Pearl Solutions (Dave Wallace): The standard enables multi-vendor EDA tool use for CDC/RDC error-free verification, with participation to meet user needs.
- Google (Dammy Olopade): The milestone involves innovation and collaboration, with expected impact on design and EDA quality and time to market.
- Intel (Lee Fueng Yap): The standard closes gaps in CDC/RDC integration through industry collaboration.
- NVIDIA (Ping Yeung): The standard allows IP verified with one tool to provide abstraction for hierarchical verification in heterogeneous environments.
- Qualcomm (Suman Chalana): The release standardizes interfaces for constraint specification and heterogeneous IP integration, improving efficiency, accuracy, and tool alignment.
- Renesas (Satoshi Shibatani): The release addresses long-standing CDC/RDC challenges in IP adoption and SoC integration.
- Siemens EDA (Farhad Ahmed & Abdul Moyeen): Standardization of hierarchical data models supports customer and IP vendor collaboration, with commitment to tool support.
- ST Microelectronics (Jean-Christophe Brignone): The standard marks a change in SoC CDC-RDC verification strategy, enabling common IP modeling and broad adoption for interoperability.
More details are available on the Accellera Clock Domain Crossing Working Group page.
