Hyperscalers and Purpose-Built Chips: Insights from Siemens' Jean-Marie Brunet on Future Trends

Global Semiconductor Landscape: Siemens VP Jean-Marie Brunet Discusses Capacity Expansion, Custom Silicon Trends, and Verification Innovations.
In a recent exclusive interview with EEHerald at the DVCon India 2025 conference in Bangalore, Jean-Marie Brunet, Vice President and General Manager of Hardware-Assisted Verification at Siemens Digital Industries Software, shared his insights on the evolving semiconductor industry. Brunet, a veteran with over two decades in electronic design automation (EDA), highlighted the surge in wafer capacity, the rise of hyperscalers developing custom silicon, and Siemens' cutting-edge solutions to tackle verification challenges as chip nodes advance to 2nm and beyond. The discussion underscores the industry's push toward geopolitical diversification and software-driven innovation amid growing complexities in design and validation.

Surging Wafer Capacity and Geopolitical Redistribution  
Brunet emphasized a "tremendous need for additional wafer capacity" driven by global geopolitical shifts. He pointed to investments in advanced nodes like 2nm and 3nm by major players including Intel, Samsung, TSMC, and emerging entrants such as Japan's Rapidus. "It's good to see Japan investing significantly in fabs and advanced nodes," Brunet noted, adding that TSMC maintains its lead in volume and technology, while U.S. expansions by TSMC ...