Coverify’s Swadeshi EDA Tools Empower India’s MSMEs in Chip Design Revolution

Coverify’s Puneet Goel Unveils Indigenous EDA Solutions to Support India’s Chip Design Surge
At DVCon India 2025, Puneet Goel, CTO and Founder of Coverify, shared a compelling vision for reducing chip design barriers for India’s Micro, Small, and Medium Enterprises (MSMEs) through innovative, indigenous electronic design automation (EDA) tools. In an exclusive interview with EEHerald, Goel discussed the high costs of chip design, the transformative potential of open-source RISC-V verification, and Coverify’s “Swadeshi EDA” approach to empower India’s burgeoning semiconductor ecosystem. His insights, presented amid discussions at Semicon India and DVCon, highlight how niche EDA players can drive India’s ambition to become a global hub for chip product development.

Tackling High Design Costs with Swadeshi EDA  
Goel emphasized that while the arrival of fabrication facilities in India is a significant step, it addresses only part of the challenge for MSMEs entering the chip design space. “For a 28nm fab, the design cost can reach $45 million,” he noted, with verification alone accounting for 50 to 70% of that expense due to the high cost of traditional EDA tools. This creates a formidable barrier for smaller companies. Coverify’s mission, through its “Swadeshi EDA” i...