NEO Semiconductor Unveils X-HBM Architecture with 32K-Bit Data Bus for AI Chips

NEO Semiconductor has introduced the Extreme High Bandwidth Memory (X-HBM) architecture, designed for AI chips. The X-HBM features a 32K-bit wide data bus and a potential density of 512 Gbit per die, offering 16X greater bandwidth or 10X higher density compared to traditional HBM.

Built on NEO’s 3D X-DRAM architecture, X-HBM addresses bandwidth and density limitations in current memory technologies. In contrast, HBM5, expected around 2030, is projected to support a 4K-bit data bus and 40 Gbit per die, while HBM8, anticipated around 2040, is expected to reach 16K-bit buses and 80 Gbit per die.

The X-HBM architecture supports faster data transfer between GPUs and memory, enhances GPU performance for AI workloads, and reduces power and hardware requirements for AI infrastructure.

Andy Hsu, CEO of NEO Semiconductor, will present the X-HBM technology in a keynote at FMS: the Future of Memory and Storage on August 6, 2025, at 11 a.m. PST. The event, held August 5-7 at the Santa Clara Convention Center, will also feature NEO Semiconductor at booth #507.