Nano-ribbon/sheet Transistors in 2nm: Intel's Patent US20250212463A on Metal-All-Around Contact Structure for dense VLSI Semiconductor Chips

Interesting patent on fabricating 2nm and lower node semiconductor chips: The U.S. Patent Application Publication 20250212463, filed by Intel Corporation on December 20, 2023, and published on June 26, 2025, introduces a novel fabrication method and integrated circuit (IC) structure featuring a metal-all-around contact structure coupled with source or drain (S/D) regions. Invented by Robin Chao and colleagues, this innovation addresses challenges in scaling ICs, particularly the increased resistance due to shrinking contact areas in densely packed semiconductor devices.

The disclosed IC structure includes a doped semiconductor region integrated within a stack of nanoribbons, with first and second portions of the nanoribbons contacting opposite sides of the S/D region. A conductive material envelops portions of the S/D region between these sides, positioned in the same layer as at least one nanoribbon. This configuration forms a continuous conductive layer that wraps around the S/D region, enhancing contact area and reducing resistance without significantly increasing capacitance or compromising channel stress. An optional interface material, such as titanium silicide, may be included between the doped semiconductor and conductive material to further lower contact resistance, while an insulating liner may encase the conductive material for electrical isolation.
The ...