Mirabilis Design has entered into an OEM agreement with Cadence Design Systems to integrate VisualSim Architect into Cadence’s system design portfolio. VisualSim offers system-level modeling, architectural exploration, and performance analysis for semiconductor and system design teams globally.
VisualSim enables designers to create executable models of complex systems, including digital, RF, analog, network, and software components, as well as semiconductors with processors, memory hierarchies, interconnects, and software applications. These models allow engineering teams to evaluate architectural decisions such as core count, network bandwidth, RF jitters, interconnect topology, and task mapping based on power, latency, throughput, and resource utilization.
Through this agreement, Cadence customers gain access to VisualSim’s capabilities, which include:
Exploring architectural trade-offs without low-level coding
Optimizing performance and power in complex SoCs and systems
Simulating software and hardware interactions before hardware instantiation
Identifying bottlenecks in compute, storage, and communication early in the design process
Yogesh Goel, Corporate Vice President of the System Design Group at Cadence, stated, “Our customers are building increasingly complex systems that demandrequire early and accurate analysis of performance, power, and resource utilization. What makes this agreement so strategic is that VisualSim brings a level of modeling efficiency and system insight that traditional, code-intensive tools struggle to match. This enables faster iteration, better collaboration across teams, and ultimately, more confident architectural decisions early in the design flow.”
Deepak Shankar, Founder of Mirabilis Design, commented, “Partnering with Cadence is a significant strategic leap forward in expanding the reach and impact of VisualSim. Cadence’s leadership in the EDA industry and strong customer relationships will make it significantly easier for system architects to adopt performance and power modeling as part of their design methodology. This agreement validates our mission to normalize system-level design exploration and accelerates our vision of enabling better, faster, and more energy-efficient products through early architectural decisions.”
VisualSim provides:
Graphical modeling and simulation, reducing the need for SystemC or C++ programming
A library of pre-validated IP blocks, including processors, memory controllers, interconnects, network protocols, and AI accelerators
Simultaneous analysis of performance, power, and timing across workloads
Integrated task schedulers and software mapping for early hardware/software co-design
The tool is designed for teams developing AI/ML processors, autonomous systems, 5G edge devices, and hyperscale computing platforms.
