New 3D fabrication process integrates Gallium Nitride transistors onto silicon chips

Researchers from MIT and other institutions have developed a new method to integrate high-performance gallium nitride (GaN) transistors onto standard silicon CMOS chips. The process is low-cost, scalable, and compatible with existing semiconductor foundries, addressing the high cost and specialization challenges that have limited GaN’s use in commercial applications.
The technique involves fabricating numerous small GaN transistors on a GaN wafer, cutting them into individual dielets (240 by 410 microns), and bonding them onto a silicon chip using copper-to-copper bonding at temperatures below 400 degrees Celsius. This low-temperature process preserves the functionality of both materials and avoids the use of costly gold, which requires higher temperatures and specialized facilities. The copper bonding method also offers better conductivity.
A specialized tool was developed to handle the precise integration, using a vacuum to position the dielet and advanced microscopy to align it with nanometer accuracy before applying heat and pressure for bonding. The process uses minimal GaN material, reducing costs while enabling performance enhancements from compact, high-speed transistors. Spreading the GaN transistors across the silicon chip also helps lower system temperatures.
The researchers demonstrated the method by fabricating a power amplifier, a key component i...