3D semiconductor: Advancing SRAM scaling with 3D integration of 2D MoS₂ FETs

Static Random-Access Memory (SRAM) is a cornerstone of modern computing, critical for cache memory, buffers, and registers due to its high-speed performance and low power consumption. However, scaling SRAM to advanced semiconductor technology nodes faces significant hurdles, with traditional planar designs encountering limitations such as increased parasitic capacitances, higher wire resistances, and exacerbated leakage currents. These challenges impede performance, area efficiency, and energy consumption in silicon-based SRAM designs. A recent study, published in Nature Communications (Volume 16, Article 4879, 2025), presents a transformative approach to reinstating SRAM scaling by leveraging three-dimensional (3D) integration of field-effect transistors (FETs) based on monolayer molybdenum disulfide (MoS₂) semiconductor material. Conducted by a team from The Pennsylvania State University, this work demonstrates significant reductions in SRAM cell area, offering a promising path for high-density, high-performance memory solutions.

SRAM’s critical role in high-performance processors is undeniable, often occupying up to 50% of a processor’s die area. However, recent scaling efforts have shown diminishing returns. For instance, SRAM cell size in TSMC’s N3 process is only about 5% smaller than in its N5 process, indic...