Analog's ascent and AI's future: A deep dive into VLSI SATA 2025

By Dr Javed GS, Architect and Analog IP Design Manager, Intel Foundry

Bengaluru, India – The halls of VLSI SATA 2025 at Amrita Vishwa Vidyapeetham, Bangalore Campus buzzed with innovation and insightful discourse today, May 23rd, as the conference delved into the cutting edge of VLSI design and its profound implications for the future of technology. About 350+ papers were submitted, and 50+ papers were accepted for presentation with a 17% acceptance rate, emphasizing on the quality of the papers submitted.

For me, it was a particularly eventful day, filled with the dual roles of session chair and panellist, offering a panoramic view of the industry's current trajectory and its most pressing challenges.

My day began by chairing two dynamic paper presentation sessions, each showcasing four research papers. The sheer breadth of the presented work were truly impressive, highlighting the academic pursuit of efficiency, speed, and novel architectures in VLSI. From advanced circuit designs to innovative fabrication techniques, the presentations offered a glimpse into the future of integrated circuits.

I e...