Cadence announced a significant expansion of its design IP portfolio optimized for Intel 18A and Intel 18A-P technologies. This expansion underscores Cadence’s leadership in driving innovation for AI, high-performance computing, and advanced mobility applications through its strategic partnership with Intel Foundry.
Cadence has collaborated closely with Intel Foundry to design and optimize a comprehensive range of solutions that fully leverage the innovative features of the Intel 18A/18A-P nodes, including RibbonFET Gate-all-around transistors and PowerVia backside power delivery network. This collaboration enables joint customers to achieve exceptional power, performance, and area efficiencies, accelerating time to market for cutting-edge system-on-chip designs. Expanded Portfolio: Cadence’s design IP portfolio now includes advanced solutions such as 224G SerDes for Universal Accelerator Link and Ultra Ethernet, DDR5 – 12.8G with MRDIMM Gen2 support, and Universal Chiplet Interconnect Express (UCIe) 1.1 48G.
AI-Driven Solutions: Certified AI-driven digital and analog/custom EDA solutions for Intel 18A technology PDK, delivering optimized PPA.
Advanced Packaging: Co-developed advanced packaging reference design flow for Intel Foundry’s EMIB and EMIB-T technology, certified for the latest PDK.
Early Engagement: Ongoing early design technology co-optimization for Intel 14A-E.
Founding Member: Cadence joins the Intel Foundry Chiplet Alliance as a founding member.
“Cadence is at the forefront of facilitating next-generation AI, HPC, and mobility designs with Intel 18A and 18A-P technologies. Our collaboration ensures that our mutual customers can leverage our robust design IP and AI-driven digital and analog/custom solutions for unparalleled performance and efficiency,” said Boyd Phelps, senior vice president and general manager of the Silicon Solutions Group at Cadence. “Our expanded design IP portfolio for Intel Foundry builds on our commitment to delivering best-in-class silicon solutions, and our advanced implementations of leading standards are key to achieving scalable, high-performance designs.”
Suk Lee, vice president and general manager of the Ecosystem Technology Office at Intel Foundry, added, “As we optimize solutions through our ongoing collaboration, the combination of Cadence's innovative IP solutions and Intel 18A and 18A-P technologies delivers advantages for AI/ML and HPC applications. Working together, we are accelerating the development of high-performance solutions, including for chiplets, that meet the evolving needs of the industry and empower our mutual customers to drive PPA efficiencies and accelerate time to market for their innovative next-generation SoC designs.”
