Synopsys and TSMC are working together to provide electronic design automation (EDA) and intellectual property (IP) solutions for TSMC’s advanced process nodes and packaging technologies, supporting AI chip design and 3D multi-die systems. Their collaboration includes certified digital and analog design flows for TSMC’s A16 and N2P processes, enabled by Synopsys.ai, with initial EDA flow development for the A14 process underway. They are also certifying tools for TSMC’s N3C technology, building on existing N3P solutions.
The Synopsys 3DIC Compiler, certified for TSMC’s CoWoS technology, supports 3Dblox and handles 5.5x-reticle interposer sizes for high-density 3D stacking. This enables high-performance computing (HPC) and AI chips with wafer-on-wafer and chip-on-wafer packaging. The compiler provides a unified environment for feasibility studies, prototyping, floorplanning, and high-throughput routing, integrating multi-physics analysis for power, thermal, and signal integrity with Ansys simulation technologies.
Synopsys’ IC Validator, certified for A16 and N2P processes, supports physical verification, including Design Rule Checks and Layout Versus Schematic checking. Its elastic architecture scaled PERC rules for TSMC N2P electrostatic discharge verification, improving turnaround time. The IC Validator 3DIC solution is also certified for 3Dblox.
Synopsys offers IP solutions for TSMC’s N2/N2P processes, including standards like 1.6T Ethernet, PCIe 7.0, UCIe, HBM4, USB4, DDR5, LPDDR6/5X/5, and MIPI, along with embedded memories, logic libraries, and IOs. These have been deployed in thousands of designs, supporting HPC, edge, and automotive applications. Synopsys has also introduced UALink and Ultra Ethernet IP, built on its PCIe and Ethernet IP, with its 224G PHY IP demonstrating interoperability for optical and copper connections.
The collaboration aims to provide certified flows and IP to help customers meet design targets and accelerate time to market for advanced system-on-chip (SoC) and multi-die designs.
