Dnotitia has announced that the first ASIC samples of its Vector Data Processing Unit (VDPU) have returned from fabrication, with chip-level characterization now underway. At AI Infra Summit 2026, held September 15-17 at the Santa Clara Convention Center, the company showcased a server-scale VDPU architecture designed to handle vector retrieval workloads, the kind of similarity searches used in retrieval-augmented generation (RAG) and agentic AI, where AI systems repeatedly search and verify information.
This showcase followed the company's first public demonstration of its VDPU chip and accelerator card at the Future of Memory and Storage (FMS) 2026 event, where Dnotitia received a Best of Show award, marking a step forward from chip-level demonstration to full server-scale evaluation.
On Dnotitia's FPGA-based evaluation platform, a server equipped with four VDPU cards delivered up to 5.77 times the vector-search throughput of the same software running on a dual-socket, CPU-only server, while maintaining equal or better recall, meaning the accuracy of retrieved results. In a workload involving 4,096-dimensional multimodal data, the VDPU reduced host CPU usage during index building by 92% and host memory usage by 73%, freeing up those resources for other application use. All of these performance figures were measured on the FPGA platform and don't represent final performance once the ASIC version ships.
Se-Hyun Yang, chief technology officer of Dnotitia, said agentic AI is shifting the AI infrastructure bottleneck away from model computation and toward retrieval. He said that as AI models search and verify information repeatedly, retrieval needs its own dedicated processing layer, and that VDPU is designed to give CPU capacity back to applications while keeping GPU high-bandwidth memory (HBM) focused on running the AI model itself. He said that at AI Infra Summit, the company showcased VDPU at server scale and opened discussions with infrastructure partners around evaluation and integration.
The FPGA platform has been validated with popular vector-search software including FAISS, Milvus, and hnswlib, across several indexing methods including brute-force k-nearest-neighbor (KNN), IVF, NSW, and HNSW. Beyond the software already ported to the FPGA platform, Dnotitia plans to support a broader range of vector libraries and databases on the final ASIC, so that VDPU can integrate with the environments customers already use.
Dnotitia's first-generation VDPU ASIC is currently undergoing chip-level characterization, with plans to begin ASIC-based VDPU evaluations in the fourth quarter of 2026. The company is targeting up to 10 times the vector-search performance of a CPU-based server with its final ASIC-based VDPU server.
During the summit, Yang presented a talk titled "Rethinking AI Infrastructure with Dedicated Vector Silicon," outlining the architecture and performance results behind VDPU. Dnotitia also met with prospective customers and infrastructure partners at Booth 205 to discuss VDPU evaluations, proof-of-concept projects, and potential integration into existing server, storage, and AI infrastructure.
Following the event, the company continues discussions with server, storage, memory, and semiconductor companies, along with vector database providers and AI framework developers, as it expands server-scale VDPU evaluations and prepares for ASIC-based evaluation in the fourth quarter of 2026.
