Researchers from CEA-Leti and Spintec in Grenoble, along with C2N and Université Paris-Saclay, have demonstrated a hybrid hardware system that combines hafnium-oxide memristors with stochastic magnetic tunnel junctions (SMTJs) to solve difficult combinatorial optimization problems, meaning problems that involve finding the best solution among an enormous number of possible combinations.
Published in Nature Communications under the title "Intrinsic Annealing in a Hybrid Memristor-Magnetic Tunnel Junction Ising Machine," the research introduces a built-in annealing mechanism, annealing being the process of gradually reducing randomness in a search to settle on a good solution, that could point toward more compact, faster, and energy-efficient hardware accelerators for this type of problem.
Ising machines are specialized hardware built to search for optimal solutions across vast numbers of possibilities. They work by repeatedly adjusting binary variables until the system settles into a low-energy configuration that represents a good balance among a problem's constraints. Compared to conventional approaches to this kind of local-search optimization, the research team's design aims to reduce how much data needs to move around and how many explicit digital instructions are needed, by instead relying on the physical behavior of the nanoscale devices themselves to perform key operations.
Louis Hutin, co-principal investigator on the project and a senior scientist at CEA-Leti, compared the optimization process to guiding a marble toward a target pocket on a tilted maze board. He explained that the tilt naturally pulls the marble downhill, but that path can sometimes lead to a dead end, and a small shake gives it enough energy to escape and try another route. In this system, he said, that "shake" comes from the natural random fluctuations of the magnetic tunnel junctions, with its strength controllable through how they're coupled to the memristor network.
The research addresses combinatorial optimization broadly, a computational challenge relevant to logistics and transport routing, power grid management, industrial scheduling and chip design, and hardware acceleration for scheduling and resource allocation in computing systems. Gains in solving these problems more efficiently can translate into real savings in time, energy, and resources across industries.
In this project, the machine carried out key steps of a local-search algorithm using dedicated physical hardware components rather than general digital processing, reducing both data movement and the number of explicit digital instructions needed to run the algorithm.
Mohammed Akib Iftakher, a doctoral researcher at CNRS, C2N, and Université Paris-Saclay, and Hugo Levices, a doctoral researcher at CEA-Leti, both co-first authors on the paper, said the core challenge was getting two very different device technologies to work together within a controlled computing loop. They explained that memristors store the structure of the problem being solved, while the stochastic magnetic tunnel junctions provide the variables that fluctuate and update over time. They said demonstrating that this hybrid system can solve real graph-optimization benchmark problems represents an important step beyond simply showing that the individual devices work in isolation.
The project also showed that these hybrid nanotechnologies can be combined into a functioning optimization accelerator rather than treated as separate, disconnected components. Because memristors, magnetic tunnel junctions, and standard CMOS circuitry are all compatible with advanced chip integration techniques, the researchers say this points toward compact, fast, energy-efficient hardware for this type of optimization.
A central challenge in optimization hardware is managing "stochasticity," meaning the random fluctuations needed to explore different possible solutions. Early in the search process, high randomness helps avoid getting stuck in suboptimal solutions, while later stages need more stability to settle on a final answer. The team demonstrated a system where the two nanotechnologies naturally work together to manage this: memristors store the problem's underlying graph, meaning the connections describing how different variables affect each other, while the SMTJs act as probabilistic yes/no variables that fluctuate due to natural thermal noise. Because these two components are closely linked, adjusting the read voltage applied to the memristor array progressively reduces randomness over the course of the search, providing a built-in annealing effect without requiring much additional supporting circuitry.
This tight coupling offers a natural way to achieve annealing without needing a separate, heavy control system managing every step of the update process. While the current prototype relies on external feedback for measurement, the underlying design points toward a fully integrated version that would minimize data movement and digital instruction overhead even further.
The prototype was tested against concrete graph-optimization benchmark problems, consistently finding the best possible solution for a 24-vertex weighted MAX-CUT problem and a 10-vertex, three-color graph-coloring problem. All measurements were taken at room temperature and without any external magnetic field applied.
While the current device processes updates sequentially, the researchers point to significant potential for speed improvements in a fully integrated version. By taking advantage of massive parallelism, nanosecond-scale switching speeds, and direct coupling between the memristor array and the magnetic junctions, eliminating the delays that come from converting between analog and digital signals, the approach could eventually run orders of magnitude faster than current electronic Ising machines.
This work brings together two complementary nanotechnologies, memristors for dense data storage and SMTJs for thermally driven randomness, into a single computing architecture. Both components are compatible with CMOS manufacturing and can be integrated into the back-end-of-line layers of a chip, supporting the kind of vertical 3D integration considered essential for future scaling.
Damien Querlioz, co-principal investigator on the project and a research director at CNRS, said the key point isn't simply that the team combined two nanotechnologies together, but that they can interact directly and help guide the search process, without forcing the system to translate every update back and forth through digital electronics.
Image: Artist’s view of intrinsic annealing in a hybrid ReRAM-SMTJ Ising machine. The maze on the left illustrates a search process in which fluctuations first help explore possible solutions. As the signal from the ReRAM array progressively dominates this randomness, the system settles into a stable configuration representing a good solution. The circuit schematic on the right evokes the hardware loop linking the ReRAM crossbar to stochastic magnetic tunnel junctions.
Looking ahead, the team plans to move from proof-of-concept experiments toward more scalable systems. Priority steps include integrating control electronics closer to the devices themselves, ideally on the same chip or within 3D stacked structures, testing larger problem sizes, and taking advantage of genuine parallel operation. Future work will focus on benchmarking speed and energy use against conventional computing approaches to quantify the actual performance gains.
