VLSI design: NEBULA, iJTAGServer and Cadence Incisive Enterprise Simulator interoperate

Intellitech has announced interoperability between its NEBULA silicon debugger, iJTAGServer and Cadence Incisive Enterprise Simulator. The iJTAGServer acts as a bridge linking Intellitech's open standards based silicon debugger with Incisive Enterprise Simulator. The solution enables IP developers to create IEEE 1149.1 compliant documentation of "Silicon Instruments" - JTAG accessible IP blocks - and get validation metrics on the documentation and code quality via Incisive pre-silicon. The pre-validated documentation can then meet the System-on-Chip (SoC) integrator's requirements for IP blocks that use IEEE 1500 style wrappers connected to the IEEE 1149.1 Test Access Port. The Intellitech NEBULA software reads IEEE 1149.1-2013 compliant models which describe the instrument registers and wrappers abstractly. This enables the use of IEEE 1149.1-2013 Procedural Description Language (PDL) to perform transactions to and from the Silicon Instrument registers in simulation via the iJTAGServer software bridge to Incisive Enterprise Simulator; as would be done post-silicon in a real SoC. IEEE 1149.1-2013 PDL is used as a complement to SystemVerilog for verification, where it has specific capabilities targeted for 1149.1/JTAG style serially accessible silicon instruments. For instance, PDL enables tools to manage the internal scan access to the Silicon Instrument through IEEE 1...