Low power VLSI design manual co-authored by ARM, Renesas and Synopsys

Engineers from Synopsys, ARM and Renesas have co-authored a manual on Verification Methodology for Low Power (VMM-LP). The VMM-LP book documents the common causes of low power bugs, provides rules and guidelines for low power verification, specifies a SystemVerilog base class library facilitating the setup of a reusable verification environment, and recommends assertions and coverage techniques to accomplish comprehensive low power verification.

This book includes real-world low power verification experience by 30 companies. Content of this book builds on the methodology originally published in the proven Verification Methodology Manual for SystemVerilog book developed by ARM and Synopsys. DVCon event attendees which going to be held in San Jose on February 24, 2009 are provided with a tutorial on this subject.

Low power design consumes more sleepless nights for VLSI designers and verification is major challenge, but the skills are must, so is the necessity of publications such as these.

Here are few comments about this book.

"The task of verifying low power designs presents a significant challenge for today's verification engineers, as most are not yet well-trained on low power concepts," said Jianfeng Liu, senior low power verification methodology engineer at Samsung Electronics. "The Verification Methodology Manual for Low Power is a timely and...