M31 Technology validated its MIPI M-PHY v5.0 IP on a 4nm process node, with ongoing development for the 3nm node.The validation covers silicon-proven MIPI M-PHY v5.0 IP compliant with MIPI Alliance specifications. It supports per-lane data rates up to 23.32 Gbps in HS-G5 (High Speed Gear 5) mode, which doubles the performance of the prior HS-G4 generation.
The IP includes adaptive equalization (Adaptive EQ) and multi-amplitude signaling to maintain signal integrity and achieve a low bit error rate (BER) at high rates. An optimized hibernate mode supports extended battery life in devices by balancing performance and power use.
M31 offers a complete UFS solution that includes the physical layer (PHY), a JEDEC-compliant UFSHCI v4.1 controller IP, and a UniPro control layer IP. This setup aims to reduce integration complexity for system-on-chip (SoC) designs. The solution incorporates ISO 26262 functional safety design processes and certification for automotive and high-reliability applications.
The announcement addresses performance needs in flagship smartphones, automotive smart cockpits, and AI edge computing devices, where data throughput demands are increasing due to AI and autonomous driving technologies.
Jerome Hung, Vice President of R&D at M31, stated: “In the wave of AI deployment and automotive intelligence, M31 leverages its deep expertise in high-speed interface IP to deliver silicon-proven M-PHY v5.0 performance on 4nm. By combining this with a fully integrated UFS 4.1 controller solution, we continue to expand our presence in advanced process technologies and automotive safety standards, positioning M31 as a trusted technology partner for next-generation high-speed storage platforms.”
