Ausdia Introduces Timevision OneSource for Constraint Translation at DAC 2025

Ausdia, a provider of design constraints verification and management solutions, launched Timevision OneSource at DAC 2025, the Chips to Systems Conference. The technology addresses challenges in maintaining hand-crafted timing constraints after optimization tools transform chip designs.
Timevision OneSource tackles issues caused by optimization engines that alter hierarchies, restructure interfaces, duplicate elements, and perform transformations like flop banking and cloning. These changes, while improving power, performance, and area (PPA), make original SDC constraints incompatible with the modified design. OneSource automatically translates these constraints to align with post-optimization netlists, eliminating manual adaptation.
The technology preserves source SDC constraints for signoff checks and generates chip-level constraints compatible with post-optimization databases. Its features include automated translation, preservation of readable constraint files, compatibility with full-chip netlists, verification of translation accuracy, and integration across pre- and post-optimization design flows.
OneSource integrates with Ausdia’s Timevision platform, which supports timing constraints for designs with over 1 billion cells and thousands of clocks, covering pre-synthesis to signoff timing. The platform addresses challenges in AI and large SoC designs, inc...