Creonic introduces oFEC Codec IP core for high-speed networking in ASIC and FPGA applications

Creonic GmbH, a provider of IP cores for ASIC and FPGA applications, has released its new oFEC (Open Forward Error Correction) codec IP core, supporting next-generation optical and high-speed communication systems. The core is available for both ASIC and FPGA configurations.

The oFEC core is designed for ultra-fast data transmission in hyperscale data centers, high-performance computing, and advanced transport networks. It achieves up to 800 Gbit/s on advanced ASIC technology nodes and up to 10 Gbit/s on FPGA, offering a scalable solution for prototyping. The core integrates with Creonic’s existing FEC portfolio and supports LDPC-based standards, including 25G/50G Ethernet, 100G/400G/800G links, and emerging optical transport standards.
The core features low latency and high energy efficiency, with compatibility for streaming or frame-based architectures. Creonic provides comprehensive technical documentation and engineering support, adhering to its ISO 9001:2015-certified development process.