AMD new Spartan UltraScale+ FPGA consume 30% less power than its previous generation

AMD expands its lineup of Cost-Optimized FPGAs and adaptive SoCs with the introduction of the Spartan UltraScale+ FPGA family. Engineered for cost efficiency and power-effective performance, these FPGAs cater to a broad spectrum of I/O-intensive applications at the edge. The Spartan UltraScale+ devices boast up to 30 percent lower total power consumption compared to their predecessors, coupled with a robust set of security features within the AMD Cost-Optimized Portfolio.
Flexible I/O Interfacing: Designed for edge applications, Spartan UltraScale+ FPGAs offer high I/O counts and flexible interfaces to seamlessly integrate with various devices or systems. They provide the industry's highest I/O to logic cell ratio on 28nm and below process technology, supporting up to 572 I/Os and voltage up to 3.3V for versatile connectivity. Power-Efficient Compute: Built on proven 16nm fabric, these FPGAs deliver power-efficient performance. They feature support for a wide array of packaging options, starting from a compact 10x10mm footprint, ensuring high I/O density in ultra-compact form factors. Additionally, the Spartan UltraScale+ family offers scalability from cost-optimized to high-end products. Robust Security: Equipped with advanced security features, Spartan UltraScale+ FPGAs safeguard I...