Andes Technology has introduced the latest Andes Automated Custom Extension (ACE), a framework for creating application-specific RISC-V instructions for domain-specific workloads. The latest generation is enhanced with COPILOT V7, which automates the integration of custom instructions into CPU RTL, compiler and simulator.
AI, networking, storage, automotive and edge computing applications are demanding greater performance and energy efficiency, according to Andes. While the open RISC-V ISA supports custom instruction extensions, implementing them typically requires processor design expertise and significant software toolchain development.
Andes says COPILOT has been used for low-latency control of external hardware blocks such as NPUs through ACE custom ports (ACP), special AI or DSP instructions such as exp(x), sin(x) and cos(x), and support for data types including fp8 and int4.
Key features of COPILOT V7 include ACE_RVV support for customized RISC-V vector (RVV) instructions by adding ACE capability to the RVV SIMD Engine; FRF Access, which allows ACE logic to access floating point registers; 64-bit ACE instructions, which double the bits available for encoding custom instructions; heterogeneous ACE instructions, which let each core in a cluster use only the instructions it needs to save hardware; and quad widening and narrowing support for ACE_RVV data format conversion.
Andes president and CTO Dr. Charlie Su said the framework enables designers to focus on application innovations while COPILOT builds the surrounding processor infrastructure, rather than spending months modifying CPU RTL and software tools. He said this shortens development cycles for instruction creation.
Andes is extending ACE support across its CPU family, from the compact 3-stage MCU-level D23 to the out-of-order application processor AX66. The company says integrating custom instructions directly into native CPU execution avoids latency, software overhead and memory bottlenecks common to memory-mapped coprocessors.
