Renesas Electronics Corporation has launched the industry's first 650 V GaN device with dual-side cooling, built for high-density power conversion in 800 V high-voltage DC (HVDC) AI data center architectures. The announcement was made from Tokyo on September 30, 2026. The new TP65H020G4PLSGBD D-Mode device delivers an on-resistance of 20 mΩ, one of the lowest in its class, in an ultra-compact dual-side-cooled (DSC) PQFN package that handles more power in less space. Renesas is currently sampling it to major AI data center OEMs and ODMs.
Built on the company's Gen IV Plus GaN architecture, the device is designed for the megawatt-scale demands of next-generation AI data centers and supports operation up to 700 V. It targets the 800 V DC/DC intermediate bus converter (IBC) stage that steps down to 48 V, 12 V, or 6 V, as well as the battery backup (BBU) and capacitor bank (CBU) stages of the sidecar power rack. As rack power climbs from roughly 120 kW toward megawatt scale, space and heat have become critical limits. Unlike conventional top-side-cooled packages, this device dissipates heat from both the top and bottom, lowering top-side thermal impedance by 10%, and its 8 x 8 mm PQFN footprint is 57% smaller than the existing 10 x 15 mm TOLT package.
The device carries the full strengths of Renesas' Gen IV Plus 650 V GaN technology, including low gate charge and output capacitance, a built-in freewheeling diode with minimal reverse recovery, and a high threshold voltage that works without a negative gate bias. Engineers can drive it with a standard silicon gate driver and switch into the MHz range to shrink passive components and cut overall BOM cost, with no need for a specialized E-mode driver.
John Wiggenhorn, Senior Product Line Director of High-Voltage GaN at Renesas, said customers building megawatt-scale AI data centers are running out of board space and thermal headroom before they reach their power limits. He explained that cooling the device from both sides and shrinking the footprint lets designers move more power through the intermediate bus without redrawing the board or adding cooling hardware, and that because it keeps the simplicity of the silicon gate drive customers already use, it is an extremely easy upgrade.
The DSC PQFN package was defined in collaboration with major AI infrastructure customers, giving it an industry-standard footprint for sourcing flexibility. Paired with Renesas AUX controllers, gate drivers, and MCUs, the GaN device forms a one-stop power solution for OEMs, ODMs, and hyperscalers moving to 800 V architectures.
Renesas has already validated the approach in silicon. A 6 kW, 800 V-to-48 V LLC DC transformer (DCX) reference design built on the new device and controlled by a Renesas RA6T3 MCU reaches a power density of 2.6 kW/in³, and per-module testing showed full-load efficiency 0.21% higher than an equivalent TOLT-based board. The smaller package also saves PCB space and allows a better-matched layout across the FETs, and 800 V-to-12 V and 6 V DC/DC IBC reference designs built on the same DSC 8x8 platform deliver similar gains in performance, scalability, and power density.
Renesas will showcase the device as part of its 800 V power solutions at the OCP Global Summit, October 12-15, in San Jose, California. The TP65H020G4PLSGBD is sampling today, and mass production is planned for mid-2027.
