AMD will offer the first Versal adaptive systems-on-chip (SoCs) with native support for Universal Chiplet Interconnect Express (UCIe) 1.1, an interface standard that enables low-power, high-bandwidth communication between AMD's adaptive SoCs and specialized chiplets packaged together with them.
The move reflects a broader shift in chip design: as designers look for more flexibility, higher performance, and faster development timelines, single monolithic chips are increasingly giving way to modular systems built from multiple specialized silicon components combined into one package. UCIe, an open industry standard, lets system designers combine specialized chips this way rather than redesigning an entire large monolithic SoC or building a new one for every application. This approach can reduce latency, power consumption, physical size, development cost, and complexity, while speeding up time to market and giving designers more flexibility to reuse proven chip components.
AMD's Versal RF Series devices will be the first Versal adaptive SoCs to support UCIe 1.1. They'll support up to four independent UCIe-SP (standard-package) interfaces and up to two UCIe-AP (advanced-package) interfaces, together providing multi-terabit-per-second aggregate bandwidth within the chip package. AMD plans to extend UCIe support to additional adaptive SoCs as the broader market matures. Envisioned applications for commercial or custom UCIe chiplets include RF analog front-ends (AFEs), AI acceleration, specialized compute, and co-packaged optics for fiber connectivity.
What makes the Versal RF Series distinctive, according to AMD, is that it already integrates high-resolution RF data converters, dedicated hardware IP for digital signal processing (DSP), AI Engines, and programmable logic all within a single chip, offering up to 80 TOPS of heterogeneous DSP compute while combining the functionality of six separate devices into one package, delivering significant benefits in size, weight, power, and cost, sometimes referred to as SWAP-C.
Adding UCIe connectivity is meant to expand these capabilities further by letting Versal RF Series chiplets communicate directly with co-packaged chiplets optimized for specific tasks, such as third-party RF AFEs or data converters, AI acceleration chiplets, CPUs, GPU-based specialized compute, custom security engines, communications processors, and application-specific integrated circuits (ASICs).
Historically, integrating components like RF front ends, AI accelerators, optical interfaces, memory subsystems, or custom ASICs required connecting them at the board level, which can add latency, increase power consumption, take up more space, and complicate design. UCIe instead provides a standardized way to connect chiplets directly within the same package, enabling efficient communication between different types of chips, including chips manufactured by different vendors.
AMD says the benefits of UCIe let customers build customized systems using existing, already-proven chiplets, avoiding the time and cost of redesigning large monolithic chips. Specific benefits include high-bandwidth communication between chiplets, reduced latency and improved power efficiency compared to AMD devices using board-level GTM2 serialized interfaces, the ability to reuse proven chip designs, potentially lower development costs, faster time to market, and greater design flexibility through combining different chiplets.
By adding UCIe connectivity, AMD says select Versal RF Series adaptive SoCs become a scalable chiplet platform capable of serving a broad range of next-generation RF, AI, networking, and communications applications, while also reducing size, weight, power, and cost. Production chiplets are expected to be available with select Versal RF Series devices in the fourth quarter of 2027.
