Secure Hash Algorithm-3 processing VLSI IP core within 28K gates

VlSI IP company CAST is making available a new IP core from Beyond Semiconductor for protecting the integrity of electronics transmissions. The Silicon IP is providing a secure HashAlgorithm-3 (SHA-3) IP compliant with latest cryptographic standard from the National Institute of Standards and Technology (NIST)-FIPS 202 and the SHA-3 functions in FIPS 180-4. This new IP by supporting these multiple standards offers a throughput data of 48 Mbits/MHz and also a lesser silicon space which is around 28K gates. Matjaž Breskvar, chief executive officer of Beyond Semiconductor says, “Our hardware implementation of the SHA-3 algorithm gives developers a state-of-the-art cryptographic primitive with which they can harness the advantages of hardware-based security to protect their devices against current and future threats”. “While simply implementing cryptographic primitives is not enough to ensure device security, our efficient hardware implementation of the Keccak sponge function family presents a solid foundation for any secure, future-proof design”. The IP is configurable and flexible, where VLSI engineers can optimize the solution as per the application requirements. This Hash accelerator IP can implement either fixed length or extensible output Hash in function that are provisioned by the standards SHA3-224, SHA3-256, SHA3-384, SHA3-512, SHAKE-128, and SHAKE-256. Anoth...