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  Date: 18/10/2015

FPGA video IP sub-system written C and C++ and leverages Vivado HLS

The latest 2015.3 release of the Vivado Design Suite from Xilinx helps VLSI design engineers to work at a higher level of abstraction with plug-and-play IP sub-systems. Vivado Design Suite 2015.3 release comes with new IP sub-systems for Ethernet, PCIe, video processing, image sensor processing, and OTN development. These IP sub-systems are based on industry standards such as ARM AMBA AXI 4 interconnect protocol, IEEE P1735 encryption and IP-XACT.

The configurable video processing IP sub-system supports 4K2K video pipe supporting VDMA, Deinterlacer, Chroma Resampler, and Scalar. The sub-system also source and sync DisplayPort, HDMI, and MIPI interfaces by using the automatically generated AXI interfaces and Vivado IPI.

Vivado IP Integrator (IPI) and Vivado High-Level Synthesis (HLS) tools are also enhanced in this new version supporting reuse of larger IP building blocks and associated content for faster integration and verification.

“All of these IP sub-systems will dramatically improve productivity by enabling the reuse of much larger building blocks and all content required for rapid integration and verification.” said Tom Feist, senior director of Design Methodology Marketing at Xilinx. “What is especially unique about our new video IP sub-system is that it was entirely written C and C++ and leveraged Vivado HLS. Our internal development time was about 4 months versus an estimated two years with an RTL flow, a 6X productivity improvement for the team. We will continue to see additional productivity gains in future generations. C-based IP reuse not only enables the IP sub-system to be easily ported from family to family but also enables automated re-optimization of the micro-architecture and associated RTL for next generation systems requirements and silicon characteristics.”

The Vivado Design Suite 2015.3 is available now with support for Xilinx 7 series and UltraScale devices as well as early access support for UltraScale FPGAs and MPSoCs.

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