Tabula' FPGAs to support of GigaChip Interface

FPGA chip vendor Tabula to support the GigaChip Interface, promoted by MoSys.

"Increased performance and bandwidth in the system are critical in order to meet the requirements for cutting-edge networking equipment. But, if the packet processors cannot access memory at the rates required, then the overall system performance suffers," stated John Monson, VP of Marketing for MoSys . "Memory access bottlenecks disappear, however, when standard operations are offloaded to MoSys' Bandwidth Engine through our ninety-percent efficient GigaChip Interface. We are pleased that Tabula has selected the GigaChip Interface as a key design feature, enabling Tabula devices to deliver next-generation packet processing performance."

"As a leading provider of breakthrough programmable logic solutions for today's most challenging 100G systems applications, Tabula is always looking for partnerships that offer our customers innovative, powerful solutions," said Alain Bismuth, Vice President of Marketing for Tabula. "Through our support of MoSys' GigaChip Interface and Bandwidth Engine devices, we can deliver overall memory capabilities not achievable with competing solutions."