Low power non-volatile memory IP for ID/tag chip design

Synopsys has announced the Multiple-Time Programmable (MTP) Ultra Low-Power (ULP) Non-Volatile Memory (NVM) IP for designing RFID/NFC ICs. Synopsys claims this new DesignWare AEON MTP ULP NVM IP cuts power consumption by up to 90 percent compared to the previous generation by offering a single-bit read capability, read operation down to 0.9V and peak current under 10uA during erase and programming. "The power and area reductions in Synopsys' ULP NVM IP enable us to maintain our strong position as a turn-key solution provider in the UHF RFID tag IC market," said Murilo Pessatti, CEO at Chipus. "As an analog IP company competing in the quickly evolving RFID market, we need reliable IP partners, and Synopsys has IP quality and support that we can trust. Based on our previous success using DesignWare NVM IP, we are confident that Synopsys' ULP NVM IP will enable us to continue to build competitive products that meet our customers' power and area demands." "Offering ULP NVM IP on our high-volume 180 nanometer CMOS process will enable our customers to reduce their overall system costs and meet the ultra low-power requirements of RFID and NFC tags," said Yit Loong Lai, senior vice president at SilTerra. "DesignWare NVM IP aligns well with our process technology to deliver an ideal combination of density, speed, and enduring performance to power future Internet of Things-...