Cadence’s Agentic AI, DAC 2026, South Korea's Semiconductor Boom, Intel's High NA EUV Milestone, and Intel/TSMC Revenue Surges. And a road trip.
Transcript
Segment 1: EDA Tools, Agentic AI, and Rapidus
Art: Welcome back to the EE Herald podcast, everyone. I’m Art, here with Ashish, and today we have a packed show covering the bleeding edge of semiconductor design and manufacturing. Today we’re covering Agentic AI in EDA Design, DAC 2026 that was held in California, South Korea’s Semiconductor boom, Intel's High NA EUV Milestone, and Intel/TSMC Revenue Surges.
Let’s kick things off with EDA tools and the rise of Agentic AI. Ashish, Rapidus is making massive waves in Japan, and they just announced a major collaboration with Cadence.
Ashish: They absolutely did, Art. Rapidus is on this hyper-aggressive timeline to build a 2nm foundry by 2027, backed by massive Japanese government subsidies and corporate giants like Sony and Toyota. But to get there, they need to drastically cut down design time. That’s where Cadence comes in. They are integrating the InnoStack AI Super Agent with Rapidus' AI-Agentic Design Solution, known as Raads.
Art: This isn't just standard machine learning for point tools anymore, right? We are talking about true "Agentic AI".
About this edition
We’re talking about Cadence’s Agentic AI, DAC 2026, South Korea's Semiconductor Boom, Intel's High NA EUV Milestone, and Intel/TSMC Revenue Surges. Also, a trip to Capitol Hill in DC and the Air and Space Museum in Virginia bubbled up some new developments and a significant historical insight.
SiliconBridge is a product of EE Herald. We independently explore the nexus between industry, academia and past, prevailing and potential future geopolitical architectures
