Renesas Electronics Corporation has developed a configurable ternary content-addressable memory (TCAM) on a 3nm FinFET process. The technology was presented at the International Solid-State Circuits Conference 2026 (ISSCC 2026), held February 15–19 in San Francisco.
The TCAM combines higher memory density, lower power consumption, and enhanced functional safety, making it applicable to automotive system-on-chips (SoCs). It supports flexible configurations for large-scale TCAMs, addressing demands from surging network traffic in 5G and cloud/edge computing, as well as automotive requirements under standards such as ISO 26262.
Conventional approaches using hard macros for scaling increase peripheral area, complicate timing closure, and raise search power. The new design uses an integrated hard- and soft-macro approach. Hard macros cover search key widths of 8–64 bits and entry depths of 32–128 in fine granularities. Larger configurations, such as 256-bit × 4,096 entries, combine these with tool-driven soft-macro auto-generation to form a single configurable macro. This achieves a memory density of 5.27 Mb/mm².
For search efficiency, each hard macro includes an all-mismatch detection circuit and a two-stage pipelined search. The second stage halts if the first stage shows all mismatches, reducing unnecessary energy use. In 64–256-bit × 512-entry configurations, search energy decreases by up to 71.1% with column-wise pipelined search (key partitioning for >64-bit keys) and up to 65.3% with row-wise pipelined search (no partitioning for ≤64-bit keys). A 256-bit × 512-entry configuration reaches 0.167 fJ/bit search energy and supports a 1.7 GHz search clock. The figure-of-merit (density × speed ÷ energy) is 53.8.
To meet automotive functional safety needs, the design addresses double-bit errors from soft errors in adjacent TCAM bitcells, which conventional SECDED ECC cannot correct. It employs split odd/even data buses for user data and ECC parity to increase physical separation, converting potential double-bit errors into correctable single-bit errors. A dedicated SRAM for ECC parity uses an independent address decoder from the TCAM, improving detection during writes when an incorrect address is selected.
The flexible key widths, entry depths, power reductions, and safety features suit the TCAM for automotive SoCs, as well as industrial and consumer devices requiring high-speed sensor-to-processor data exchange.
Renesas will continue advancing memory architectures for high capacity, low power, and high reliability.
