S2C MachineWare and Andes Announces RISC-V Co-Emulation Solution 2025

S2C, MachineWare, and Andes Technology announced a co-emulation solution for RISC-V based chip design. The solution combines MachineWare’s SIM-V virtual platform, S2C’s Genesis Architect and Prodigy FPGA Prototyping Systems, and Andes’ AX46MPV RISC-V CPU core for hardware and software co-verification.

The solution supports pre-silicon software development, hardware/software co-verification, system performance analysis, and custom ISA extension development and debug.

MachineWare’s SIM-V is a SystemC TLM-2.0 based full-system virtual platform. It integrates with third-party toolchains for debugging, testing, and coverage analysis. SIM-V provides instruction-accurate reference models implementing the AndeStar V5 Instruction Set Architecture, including the RISC-V Vector extension. The SIM-V Extension API allows modeling, validation, and debugging of proprietary processor enhancements with trace and introspection capabilities.

Lukas Jünger, CEO of MachineWare, stated that the co-emulation solution allows validation of hardware and software in parallel and reduces integration risks.

Andes Technology provides the AndesCore AX46MPV multicore processor. The AX46MPV is an 8-stage superscalar 64-bit RISC-V CPU supporting up to 16 cores, multi-level cache, a Vector Processing Unit with up to 1024-bit VLEN and High-Bandwidth Vector...