Andes Technology Delivers AX46MPV RISC-V Vector Core to First Customer for TSMC Tape-Out in Cloud AI Acceleration

Andes has completed final database hand-off of its AX46MPV vector processor core to its first licensee for tape-out at TSMC. Additional customer tape-outs are scheduled for Q4 2025 and throughout 2026.

The AX46MPV is the third-generation vector core in Andes’ lineup targeting cloud AI workloads. It succeeds the NX27V, deployed in Meta’s MTIA-1 in 2019, and the AX45MPV.

The core is designed to handle Transformer model functions not executed on specialized matrix engines, including LayerNorm and Softmax kernels. On these kernels, the AX46MPV achieves 30 % to 70 % performance improvement over the AX45MPV using LLVM-generated code without hardware look-up tables or dedicated functional units.

Performance gains are obtained through algorithmic optimizations and instruction-level parallelism within the RISC-V vector extension, supported by features including a re-ordering buffer and compatibility with LLVM 16 and later auto-vectorization, software pipelining, and data interleaving.

Dr. Charlie Su, Andes president and CTO, stated: “The timing is just about perfect. nVidia’s recent CPX announcement has spotlighted the move away from general purpose GPUs to more power efficient hardware accelerator-based AI infrastructure, complemented by equally efficient CPUs.”

Alex Chen, Andes director of VLSI for the AX46MPV, stated...