Cadence Adds 10 New Verification IP for UALink, Ultra Ethernet, LPDDR6, UCIe 3.0 and Other AI-Focused Interfaces
Cadence Design Systems has released 10 new Verification IP (VIP) solutions targeting interfaces used in AI-driven designs.
The new VIP cover the following protocols and specifications:
- Ultra Accelerator Link (UALink)
- Ultra Ethernet (UEC)
- LPDDR6
- UCIe 3.0
- AMBA CHI-H
- Embedded USB v2 (eUSB2)
- MIPI UniPro 3.0
- MIPI M-PHY 6.0
- MIPI CSE 2.0
- ONFI 5.2
Each VIP includes a UVM SystemVerilog test suite and is designed to support verification of designs compliant with these standards.
The additions expand Cadence’s existing Verification IP portfolio, which is used by multiple customers for protocol compliance testing.
Ziyad Hanna, Corporate VP at Cadence, stated: “The fast-evolving AI market creates a new level of requirements for higher bandwidth and lower power, resulting in a new set of interfaces to address these needs. Cadence is committed and proud to provide the Verification IP and tools to enable the new generation of AI SoCs.”
The new VIP solutions integrate with Cadence’s verification tools, including Palladium Z3 emulation, Protium X3 prototyping, Xcelium simulation, Jasper Formal Verification Platform, Helium Virtual and Hybrid Studio, and Verisium AI-Driven Verification Platfo...