YES Secures Orders for VeroTherm and VeroFlex Systems to Support AI-Driven 3D Chip Stacking

Yield Engineering Systems (YES) announced receiving multiple orders for its VeroTherm and VeroFlex reflow systems from a major memory supplier. These systems are designed to enable 3D stacking of memory and logic chips for high-performance AI accelerators, particularly for large language model (LLM) applications.

The VeroTherm and VeroFlex platforms support advanced packaging by providing thermal uniformity and mechanical reliability for ultra-fine pitch interconnects. They facilitate fluxless solder and mass reflow processes in a low vacuum environment for wafers and panels, enabling sub-10μm micro-bump structures. These capabilities are critical for manufacturing stacked logic and high bandwidth memory (HBM) used in AI accelerators.

Rezwan Lateef, President of YES, stated, “The VeroTherm and VeroFlex process platforms deliver enhanced thermal uniformity and mechanical reliability for advanced packaging applications requiring ultra-fine pitch interconnects. Our validation studies demonstrate zero-defect reflow performance with no evidence of bump fracture or structural collapse at pitches as aggressive as 10μm. The proprietary process architecture achieves deterministic solder joint formation while maintaining statistical process control metrics that enable high-volume manufacturing with optimized cost-per-unit economics.”

Alex Chow, S...