MSquare technology debuts ML100 IO die chiplet at COMPUTEX 2025

COMPUTEX 2025, held at the Taipei Nangang Exhibition Center, began on May 20 and runs through May 23, hosting over 50,000 professionals from 34 countries. MSquare Technology is presenting its ML100 IO Die, a chiplet solution for AI system-on-chip (SoC) architectures, focusing on chiplet integration and high-speed interconnect technology. The event, themed “AI Next,” emphasizes AI & Robotics, Next-Gen Tech, and Future Mobility. The ML100 IO Die addresses bandwidth, power, and cost limitations in traditional SoC integration as AI models grow.

The ML100 IO Die, designed for data centers and high-performance computing, incorporates UCIe protocol and HBM3 memory interface technology. It separates SoC and HBM through chiplet partitioning to optimize die area, cost, and power consumption while increasing memory bandwidth. The chiplet supports a 32Gbps UCIe PHY with a peak bandwidth of 1TB/s and is suited for AI accelerators, inference engines, and high-performance computing chips. The ML100 received the “Best IP of the Year” award from EE Awards Asia 2024.
Founded in 2021, MSquare Technology, led by former AMD, Apple, and MediaTek professionals, develops high-speed interface IP and chiplet solutions for protocols including UCIe, HBM, ONFI, LPDDR, PCIe, and USB...