AMD announced more than $10 billion in investments across the Taiwan ecosystem to expand strategic partnerships and scale advanced packaging manufacturing for next-generation AI infrastructure. The investments support development of leading-edge silicon, packaging, and manufacturing technologies. These efforts build on AMD’s chiplet architectures, high-bandwidth memory integration, 3D hybrid bonding, and rack-scale system design.
AMD is collaborating with Taiwan-based ASE and SPIL, as well as other partners, to develop and qualify next-generation wafer-based 2.5D bridge interconnect technology called Elevated Fanout Bridge (EFB). EFB architecture increases interconnect bandwidth and improves power efficiency for 6th Gen AMD EPYC CPUs, codenamed “Venice.”
AMD has also qualified the industry’s first 2.5D panel-based EFB interconnect with PTI. This technology supports high-bandwidth interconnect at scale. These packaging advancements are being applied to the AMD Helios rack-scale platform. The platform, powered by 6th Gen AMD EPYC “Venice” CPUs and AMD Instinct MI450X GPUs, is on track for multi-gigawatt deployments beginning in the second half of 2026. Leading ODM partners including Sanmina, Wiwynn, Wistron, and Inventec are involved in building Helios-based systems, along with advanced networking and the AMD ROCm open software stack.
“As AI adoption accelerates, our global customers are rapidly scaling AI infrastructure to meet growing compute demand,” said Dr. Lisa Su, Chair and CEO, AMD. “By combining AMD leadership in high-performance computing with the Taiwan ecosystem and our strategic global partners, we are enabling integrated, rack-scale AI infrastructure that helps customers accelerate deployment of next-generation AI systems.”
Partner statements confirm collaboration on manufacturing, platform integration, and packaging technologies for the Helios program and EFB solutions.
