Imec Launches First-of-Its-Kind European University Consortium on CMOS 2.0 Beyond Traditional Chip Scaling

Imec has launched a consortium with 26 European university groups to jointly work on the technology roadmap beyond CMOS scaling, designated as CMOS 2.0.

The initiative focuses on design automation and chip architecture research for the next generation of chips. It will utilize imec’s NanoIC pilot line to convert academic insights into industry-focused innovations. Future consortia are planned around advanced materials and alternative compute systems.

CMOS 2.0, a paradigm introduced by imec, extends the chipmaking toolbox beyond conventional transistor scaling and its associated challenges. It provides greater design flexibility through fine-grain wafer stacking technology, which enhances on-chip connectivity and enables higher technology heterogeneity. The approach results in tailored chips built from multiple 3D-stacked layers that perform smartly partitioned functions, creating advanced and versatile 3D-stacked platforms.

This paradigm shift carries implications for the design and optimization of computing architectures tailored to future workloads and applications. CMOS 2.0 is positioned to support next-generation energy-efficient compute systems and to affect applications ranging from general-purpose processor...