CEA-Leti Reports 400°C SOI CMOS Achievement at IEDM 2025 for 3D Sequential Integration in FAMES Pilot Line

CEA-Leti, coordinator of the FAMES Pilot Line, has fabricated fully functional 2.5 V silicon-on-insulator (SOI) CMOS devices at a processing temperature of 400 °C. These devices exhibit electrical performance equivalent to those produced using the conventional high-temperature process exceeding 1000 °C.

The development, detailed in a paper presented at the IEEE International Electron Devices Meeting (IEDM) 2025 titled “High Performance 2.5 V n&p 400 °C SOI MOSFETs: A Breakthrough for Versatile 3D Sequential Integration,” addresses a key technical limitation in large-scale 3D sequential integration (3DSI). This integration approach provides the highest interconnection density among 3D technologies, including through-silicon vias (TSV) and hybrid bonding.

The low-temperature process makes Si CMOS compatible with back-end-of-line (BEOL) fabrication, allowing transistors to be stacked above BEOL layers without damaging underlying circuitry. The transistors maintain performance and maturity levels superior to other state-of-the-art low-temperature alternatives, such as polycrystalline films, oxide semiconductors, or carbon nanotubes.

The process utilizes optimized 400 °C low-pressure chemical va...