Cadence and Alphawave Semi Separately Achieve 64 Gbps UCIe IP Tapeouts on TSMC N3P for AI Chiplet Connectivity

Cadence has completed the tapeout of its third-generation Universal Chiplet Interconnect Express (UCIe) IP solution on TSMC's N3P process technology, achieving 64 Gbps per-lane speeds.

The Cadence UCIe IP subsystem complies with the UCIe specification and supports protocols including AXI, CXS.B, CHI-C2C, PCIe, and CXL. It includes advanced error correction, lane margining, and diagnostic capabilities. Bandwidth density reaches 3.6 Tbps/mm in standard packaging and 21.08 Tbps/mm in advanced packaging. Features include self-calibrating capabilities, hardware-based bring-up without firmware intervention, streamlined clocking with integrated PLL, and operation across voltage and temperature variations.

Cadence noted prior die-to-die tapeouts starting in 2018, adoption of UCIe in 2022, and silicon demonstrations of previous generations. The IP targets AI accelerators, high-performance computing (HPC), networking appliances, and data center systems.

Source: Cadence

In a separate announcement on September 24, 2025 Alphawave Semi (recently acquired by Qualcomm) has also  shared the tapeout of its third-generation 64 Gbps UCIe die-to-die IP subsystem on TSMC's N3P process. It achieves 64 Gbps per-lane uni-direction...