Sofics Advances ESD IP on TSMC 4nm and 2nm Nodes for AI and HPC Applications

Sofics, a Belgium-based provider of semiconductor IP focused on on-chip ESD protection and interface solutions, has achieved milestones in collaboration with TSMC on advanced process nodes.

On October 21, 2025, Sofics announced the tape-out of a test chip on TSMC's N4C (4nm-class) process. The chip includes ESD protection clamps for voltages ranging from 0.75V to 3.3V, along with 1.8V and 3.3V GPIO circuits, including a 3.3V overvoltage-tolerant GPIO base cell, matched voltage regulators, and low-power regulators. These solutions target applications in mobile, automotive, high-performance computing (HPC), and AI. Sofics has been part of TSMC's Open Innovation Platform (OIP) IP Alliance since 2010, with IP now available for licensing on nodes including N16FFC, N12FFC, N7, N5, N4C, N3E, and N2P.

Earlier, on June 25, 2025, Sofics announced silicon validation of its IP on TSMC's 2nm nanosheet technology. The validated solutions provide robustness for interfaces at 0.75V, 0.9V, 1.2V, 1.5V, and 1.8V, low parasitic capacitance for high-speed applications, area reductions in GPIO cells, and GPIO circuits at 1.2V or 1.8V for legacy chip communication. These are intended for system-on-chip (SoC) and chiplet designs in AI, HPC, smartphone, and data center applications. The IP engaged input from over ten semiconductor companies and is available for licensing on TSMC 2nm.