Tower Semiconductor Launches Wafer-Scale 3D-IC CPO Foundry Technology on 300mm SiPho and SiGe BiCMOS Platforms with Cadence Design Support

Tower Semiconductor expanded its 300mm wafer bonding technology, originally developed and in mass production for stacked back-side illuminated (BSI) image sensors, to support heterogeneous 3D-IC integration across its Silicon Photonics (SiPho) and SiGe BiCMOS process platforms.

The technology enables wafer-scale stacking of different process nodes, including Photonic ICs (PICs) and Electronic ICs (EICs), into a single 3D-IC. It supports simultaneous use of multiple process design kits (PDKs) and targets applications such as Co-Packaged Optics (CPO) for data center systems.

The wafer bonding process has been demonstrated with precision alignment and reliability on 300mm wafers.

Tower has collaborated with Cadence Design Systems to extend the Cadence Virtuoso Studio Heterogeneous Integration flow for co-simulation and co-verification of multiple process technologies in a unified design environment. The updated flow is compatible with Tower’s SiPho and SiGe BiCMOS PDKs and supports die-to-wafer and wafer-to-wafer bonding applications.

Dr. Marco Racanelli, President of Tower Semiconductor, stated that the company’s experience in high-volume wafer stacking for CIS technologies has provided the foundation for this 3D integration capability on 300mm wafers.

Dr. Samir Chaudhry, VP of Customer Design Enablement at Tower Semiconductor, sa...