Latest Trends in Atomic Layer Deposition (ALD) for Semiconductor Chip Fabrication

Atomic Layer Deposition (ALD) supports semiconductor manufacturing for sub-3nm nodes, 3D architectures, and AI-enabled devices. The global ALD equipment market projects growth from USD 7.16 billion in 2025 to USD 12.30 billion by 2030, at a CAGR of 11.43%. Semiconductors account for over 68% of demand due to ultra-thin, conformal films in logic and memory chips.

Lam Research launched the ALTUS Halo tool in February 2025 for high-volume molybdenum (Mo) ALD. This supplements traditional tungsten (W) ALD with lower-resistivity interconnects in nano-scale wires, eliminating adhesion/barrier layers and reducing process steps. The tool applies to 1,000-layer 3D NAND, 4F2 DRAM, and gate-all-around (GAA) logic.

TSMC started 2nm fab construction in March 2025, using ALD for high-k gate dielectrics, transition-metal nitrides, and metal films in GAA transistors. This addresses scaling below 5nm with atomic-scale control in transistor gates and interconnects.

ALD equipment advancements target higher throughput. Batch-type systems project USD 2.5 billion by 2033 at a CAGR of 9.1%. Forge Nano began production of TEPHRA ALD cluster tools in a 2,000 sq ft cleanroom in January 2025 for the 200mm market. Spatial ALD expects 17.1% CAGR to 2030 for non-thermal deposition. SiCarrier debuted the Alishan tool in March 2025 to expand China's domestic ALD supply.

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