STMicroelectronics to Launch Next-Gen Panel-Level Packaging Pilot Line in Tours, France by Q3 2026

STMicroelectronics announced the development of a new Panel-Level Packaging (PLP) pilot line at its Tours, France facility, set to be operational in the third quarter of 2026. The initiative, backed by a $60 million investment, aims to advance chip packaging and test manufacturing technology, focusing on efficiency and flexibility for applications in RF, analog, power, and digital products.

The PLP technology uses large rectangular substrates instead of circular wafers, enabling higher manufacturing throughput and cost reduction. This approach supports the production of smaller, more powerful, and cost-effective electronic devices. The Tours pilot line will build on STMicroelectronics’ existing PLP operations in Malaysia and its global R&D network, aiming to expand PLP applications across automotive, industrial, and consumer sectors.

A multidisciplinary team, including experts in manufacturing automation, process engineering, data science, and R&D, will drive the project. The initiative aligns with STMicroelectronics’ strategic focus on heterogeneous integration, enhancing chip integration scalability and efficiency. The Tours site will leverage synergies with the local R&D ecosystem, including the CERTEM R&D center, and is part of a broader company program to reshape its global manufacturing footprint, which includes redefined missi...