Semicon India 2025 Highlights Indigenous Chip Design Innovations with RISC-V and DLI Support

Semicon India 2025, held at Yashobhoomi, showcased advancements in India’s semiconductor ecosystem, with a focus on indigenous chip design under the Design Linked Incentive (DLI) Scheme. Prime Minister Narendra Modi, accompanied by Minister of Electronics and Information Technology Ashwini Vaishnaw and Minister of State Jitin Prasada, visited exhibition stalls, emphasizing the role of startups in advancing India’s semiconductor capabilities and intellectual property creation.

The DLI Scheme has sanctioned 23 chip design projects, enabling 72 companies to access industry-grade Electronic Design Automation (EDA) tools. Startups displayed their roadmaps for System-on-Chip (SoC) solutions targeting sectors like surveillance, broadband, smart energy meters, motor control, and space applications, aligning with India’s goal of becoming a full-stack semiconductor nation.

InCore Semiconductors introduced a RISC-V-based SoC Generator Platform, reducing frontend chip design time from months to minutes. The platform, tested on TSMC’s 40nm process node, integrates six heterogeneous RISC-V cores, a custom Network-on-Chip, and a full software stack with an RTOS. InCore’s portfolio includes Azurite for low-power applications, Calcite for mid-tier embedded systems, and Dolomite, under development, for high-performance networking and edge AI.