Cadence and NVIDIA Collaborate on AI Power Analysis for Billion-Gate Designs

Cadence  announced a collaboration with NVIDIA to advance power analysis for pre-silicon AI designs using the Cadence Palladium Z3 Enterprise Emulation Platform and the new Cadence Dynamic Power Analysis (DPA) App. The technology enables hardware-accelerated dynamic power analysis of billion-gate AI designs, processing billions of cycles in two to three hours with up to 97 percent accuracy.

The solution addresses the challenge of predicting power consumption in complex semiconductors under realistic conditions, where conventional tools are limited to a few hundred thousand cycles. By leveraging hardware-assisted power acceleration and parallel processing, the Palladium Z3 Platform with the DPA App allows designers to estimate power usage, verify functionality, and assess performance before tapeout. This supports energy-efficient designs for AI, machine learning, and GPU-accelerated applications, enabling optimization during the design phase to avoid delays from over- or under-designed chips.

The DPA App integrates with Cadence’s analysis and implementation solutions, facilitating power estimation, reduction, and signoff throughout the design process. For more details, visit the Cadence Palladium web page.