UCIe Consortium Unveils 3.0 Specification with 64 GT/s Speeds and Enhanced Chiplet Interconnect Features

The Universal Chiplet Interconnect Express (UCIe) Consortium has released the UCIe 3.0 specification, an open standard for chiplet interconnects within a package, supporting data rates of 48 GT/s and 64 GT/s for UCIe-S and UCIe-A. The specification doubles the bandwidth of UCIe 2.0 (32 GT/s) to meet the demands of high-performance, modular semiconductor designs, particularly for AI and other bandwidth-intensive applications.

The UCIe 3.0 specification includes runtime recalibration for power-efficient link tuning, extended sideband channel support up to 100mm for flexible System-in-Package (SiP) topologies, and priority sideband packets for low-latency signaling. It also introduces early firmware download via the Management Transport Protocol (MTP), fast throttle, and emergency shutdown mechanisms using open-drain I/O. Continuous transmission protocols are supported through mappings for applications like SoC-to-DSP chiplet connectivity. The specification maintains backward compatibility with previous UCIe versions and offers optional manageability features for design customization.

Cheolmin Park, UCIe Consortium President and Corporate VP at Samsung Electro-Mechanics, stated that the specification enhances speed, efficiency, and manageability to support scalable multi-chip designs and foster an interoperable chiplet ecosystem. The UCIe 3.0 specification is avai...